Configurations for IDDQ-Testable PLAs

widely used in integrated circuits because they provide a simple, automated way of implementing complex Boolean functions. Often, microprocessors use PLAs to implement such functions as instruction decoding. 1,2 In its simplest form, a PLA is a highly uniform structure capable of implementing any Boolean function expressed in the sum-of-products form. The PLA structure consists of an AND plane and an OR plane. Earlier, PLAs were implemented using wired logic. A pull-up transistor (or resistor) pulls each output high. Depending on the input data on switching transistors connected to output lines, output lines are pulled low—or evaluated. For embedded applications, designers generally prefer dynamic PLAs because of their smaller area compared to static PLAs, their low power dissipation, and their greater throughput via pipelined processing. Generally , we implement them as INV-NOR-NOR-INV structures. In a typical dynamic PLA, precharge and evaluation functions replace wired logic. Figure 1 shows an example of a dynamic PLA configuration with three inputs , four product terms, and three outputs. The I DDQ test method is a powerful technique for detecting bridging defects in digital circuits; 3,4 it is incomparable in terms of quality, simplicity, and cost. At the same time, it is a relatively slow method for testing logic. Therefore, there is a strong motivation to improve defect coverage for each I DDQ measurement. With the two PLA configurations presented in this article, we attempt to achieve this goal. Traditionally, a PLA fault model consists of the following faults: • Line stuck-at faults. These include single or multiple-line stuck-at faults. The PLA fault model considers faults on input lines, product lines, output lines, input and output registers, pull-up logic, and so on. • Crosspoint faults. A crosspoint may exist at an undesirable location, or a cross-point may be missing from a desirable location. These faults are known as extra-and missing-crosspoint faults. They are also known as crosspoint growth and crosspoint shrinkage faults. • Bridging faults. These can exist among the input, product, and output lines. The model also considers bridging faults between input and product lines and between product lines and output lines. • Open faults. The model considers these on input, product, and output lines. Open faults can cause sequential behavior in CMOS logic circuits. However, this behavior is not likely in PLAs because dynamic PLAs rarely contain CMOS logic gates other than inverters. Most open faults in a PLA occur on lines …